%0 Conference Paper %1 conf/vlsid/RaghunathanAM95 %A Raghunathan, Anand %A Ashar, Pranav %A Malik, Sharad %B VLSI Design %D 1995 %I IEEE Computer Society %K dblp %P 104-109 %T Test generation for cyclic combinational circuits. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid1995.html#RaghunathanAM95 %@ 0-8186-6905-5

@inproceedings{conf/vlsid/RaghunathanAM95, added-at = {2023-09-30T00:00:00.000+0200}, author = {Raghunathan, Anand and Ashar, Pranav and Malik, Sharad}, biburl = {https://www.bibsonomy.org/bibtex/2f444b0110163f8cf52c3872a79c0f674/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/1995}, ee = {https://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512086}, interhash = {cd048e0d8a4f198d630ee8c832671ab6}, intrahash = {f444b0110163f8cf52c3872a79c0f674}, isbn = {0-8186-6905-5}, keywords = {dblp}, pages = {104-109}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T05:46:44.000+0200}, title = {Test generation for cyclic combinational circuits.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid1995.html#RaghunathanAM95}, year = 1995 }