%0 Conference Paper %1 conf/ieeehpcs/SanzoC16 %A di Sanzo, Pierangelo %A Ciciani, Bruno %B HPCS %D 2016 %I IEEE %K dblp %P 42-47 %T CPU-core frequency scaling for efficient thread scheduling in transactional memories. %U http://dblp.uni-trier.de/db/conf/ieeehpcs/ieeehpcs2016.html#SanzoC16 %@ 978-1-5090-2088-1

@inproceedings{conf/ieeehpcs/SanzoC16, added-at = {2020-06-15T00:00:00.000+0200}, author = {di Sanzo, Pierangelo and Ciciani, Bruno}, biburl = {https://www.bibsonomy.org/bibtex/24f7298ec7767e045ba081d366e6b6d97/dblp}, booktitle = {HPCS}, crossref = {conf/ieeehpcs/2016}, ee = {https://doi.org/10.1109/HPCSim.2016.7568314}, interhash = {cdc8ecfa144a125d446ee12f264197a1}, intrahash = {4f7298ec7767e045ba081d366e6b6d97}, isbn = {978-1-5090-2088-1}, keywords = {dblp}, pages = {42-47}, publisher = {IEEE}, timestamp = {2020-06-16T12:24:13.000+0200}, title = {CPU-core frequency scaling for efficient thread scheduling in transactional memories.}, url = {http://dblp.uni-trier.de/db/conf/ieeehpcs/ieeehpcs2016.html#SanzoC16}, year = 2016 }