%0 Journal Article %1 journals/vlsi/BrownKL96 %A Brown, Stephen Dean %A Khellah, Muhammad M. %A Lemieux, Guy %D 1996 %J VLSI Design %K dblp %N 4 %P 275-291 %T Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays. %U http://dblp.uni-trier.de/db/journals/vlsi/vlsi4.html#BrownKL96 %V 4

@article{journals/vlsi/BrownKL96, added-at = {2022-12-06T00:00:00.000+0100}, author = {Brown, Stephen Dean and Khellah, Muhammad M. and Lemieux, Guy}, biburl = {https://www.bibsonomy.org/bibtex/2555c1e72fb277fef4b95e944a6e952c7/dblp}, ee = {https://doi.org/10.1155/1996/45983}, interhash = {d2b227edc2cd34702f48aee0a6f35518}, intrahash = {555c1e72fb277fef4b95e944a6e952c7}, journal = {VLSI Design}, keywords = {dblp}, number = 4, pages = {275-291}, timestamp = {2024-04-08T12:07:56.000+0200}, title = {Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays.}, url = {http://dblp.uni-trier.de/db/journals/vlsi/vlsi4.html#BrownKL96}, volume = 4, year = 1996 }