%0 Journal Article %1 journals/iet-cds/BrnovicDIS19 %A Brnovic, Nevena R. %A Djurovic, Igor %A Ivanovic, Veselin N. %A Simeunovic, Marko %D 2019 %J IET Circuits Devices Syst. %K dblp %N 2 %P 131-138 %T Hardware implementation of the quasi-maximum likelihood estimator core for polynomial phase signals. %U http://dblp.uni-trier.de/db/journals/iet-cds/iet-cds13.html#BrnovicDIS19 %V 13

@article{journals/iet-cds/BrnovicDIS19, added-at = {2020-12-31T00:00:00.000+0100}, author = {Brnovic, Nevena R. and Djurovic, Igor and Ivanovic, Veselin N. and Simeunovic, Marko}, biburl = {https://www.bibsonomy.org/bibtex/2863dbb1b2ae57070e820b5c87b21aef4/dblp}, ee = {https://doi.org/10.1049/iet-cds.2018.5112}, interhash = {d43f22e9160d9496040d56013f964aac}, intrahash = {863dbb1b2ae57070e820b5c87b21aef4}, journal = {IET Circuits Devices Syst.}, keywords = {dblp}, number = 2, pages = {131-138}, timestamp = {2024-04-08T16:07:02.000+0200}, title = {Hardware implementation of the quasi-maximum likelihood estimator core for polynomial phase signals.}, url = {http://dblp.uni-trier.de/db/journals/iet-cds/iet-cds13.html#BrnovicDIS19}, volume = 13, year = 2019 }