%0 Conference Paper %1 conf/fpl/JiangLYWY14 %A Jiang, Zhenghong %A Lin, Colin Yu %A Yang, Liqun %A Wang, Fei %A Yang, Haigang %B FPL %D 2014 %I IEEE %K dblp %P 1-6 %T Exploring architecture parameters for dual-output LUT based FPGAs. %U http://dblp.uni-trier.de/db/conf/fpl/fpl2014.html#JiangLYWY14

@inproceedings{conf/fpl/JiangLYWY14, added-at = {2017-05-21T00:00:00.000+0200}, author = {Jiang, Zhenghong and Lin, Colin Yu and Yang, Liqun and Wang, Fei and Yang, Haigang}, biburl = {https://www.bibsonomy.org/bibtex/2cf73495b86c9490b4fc934a90de5396c/dblp}, booktitle = {FPL}, crossref = {conf/fpl/2014}, ee = {https://doi.org/10.1109/FPL.2014.6927470}, interhash = {d8ffa0570a9c721ed890760d03922626}, intrahash = {cf73495b86c9490b4fc934a90de5396c}, keywords = {dblp}, pages = {1-6}, publisher = {IEEE}, timestamp = {2019-10-17T19:13:37.000+0200}, title = {Exploring architecture parameters for dual-output LUT based FPGAs.}, url = {http://dblp.uni-trier.de/db/conf/fpl/fpl2014.html#JiangLYWY14}, year = 2014 }