%0 Conference Paper %1 conf/iscas/KumarSG19 %A Kumar, B. Dinesh %A Shrimali, Hitesh %A Gupta, Navneet %B ISCAS %D 2019 %I IEEE %K dblp %P 1-5 %T A 6-Bit, 29.56 fJ/Conv-Step, Voltage Scalable Flash-SAR Hybrid ADC in 28 nm CMOS. %U http://dblp.uni-trier.de/db/conf/iscas/iscas2019.html#KumarSG19 %@ 978-1-7281-0397-6

@inproceedings{conf/iscas/KumarSG19, added-at = {2022-06-23T00:00:00.000+0200}, author = {Kumar, B. Dinesh and Shrimali, Hitesh and Gupta, Navneet}, biburl = {https://www.bibsonomy.org/bibtex/21be2d60c930e561acae1c38e007a0085/dblp}, booktitle = {ISCAS}, crossref = {conf/iscas/2019}, ee = {https://doi.org/10.1109/ISCAS.2019.8702482}, interhash = {dd32560f6e254071f9712a46e1f8fbf7}, intrahash = {1be2d60c930e561acae1c38e007a0085}, isbn = {978-1-7281-0397-6}, keywords = {dblp}, pages = {1-5}, publisher = {IEEE}, timestamp = {2024-04-10T17:48:30.000+0200}, title = {A 6-Bit, 29.56 fJ/Conv-Step, Voltage Scalable Flash-SAR Hybrid ADC in 28 nm CMOS.}, url = {http://dblp.uni-trier.de/db/conf/iscas/iscas2019.html#KumarSG19}, year = 2019 }