%0 Conference Paper %1 conf/iscas/MeadeJTZ16 %A Meade, Travis %A Jin, Yier %A Tehranipoor, Mark M. %A Zhang, Shaojie %B ISCAS %D 2016 %I IEEE %K dblp %P 1334-1337 %T Gate-level netlist reverse engineering for hardware security: Control logic register identification. %U http://dblp.uni-trier.de/db/conf/iscas/iscas2016.html#MeadeJTZ16 %@ 978-1-4799-5341-7

@inproceedings{conf/iscas/MeadeJTZ16, added-at = {2022-04-09T00:00:00.000+0200}, author = {Meade, Travis and Jin, Yier and Tehranipoor, Mark M. and Zhang, Shaojie}, biburl = {https://www.bibsonomy.org/bibtex/2576b156388f4f24ddf11cf99ce68e847/dblp}, booktitle = {ISCAS}, crossref = {conf/iscas/2016}, ee = {https://doi.org/10.1109/ISCAS.2016.7527495}, interhash = {ddf4951357018bb603497de2762c0002}, intrahash = {576b156388f4f24ddf11cf99ce68e847}, isbn = {978-1-4799-5341-7}, keywords = {dblp}, pages = {1334-1337}, publisher = {IEEE}, timestamp = {2024-04-10T17:49:39.000+0200}, title = {Gate-level netlist reverse engineering for hardware security: Control logic register identification.}, url = {http://dblp.uni-trier.de/db/conf/iscas/iscas2016.html#MeadeJTZ16}, year = 2016 }