%0 Conference Paper %1 conf/iecon/RobertMCG22 %A Robert, Téo %A Monthéard, Romain %A Combet, Valentin %A Gavelle, Mathieu %B IECON %D 2022 %I IEEE %K dblp %P 1-6 %T Hardware-In-the-Loop Simulation of a High Frequency Interleaved Converter based on a Low-Cost FPGA Platform. %U http://dblp.uni-trier.de/db/conf/iecon/iecon2022.html#RobertMCG22 %@ 978-1-6654-8025-3

@inproceedings{conf/iecon/RobertMCG22, added-at = {2023-03-21T00:00:00.000+0100}, author = {Robert, Téo and Monthéard, Romain and Combet, Valentin and Gavelle, Mathieu}, biburl = {https://www.bibsonomy.org/bibtex/2b1422a53c51c11f6392b3a71820dff48/dblp}, booktitle = {IECON}, crossref = {conf/iecon/2022}, ee = {https://doi.org/10.1109/IECON49645.2022.9968950}, interhash = {dfc67ec5f00cc0763631b021e3ebb72e}, intrahash = {b1422a53c51c11f6392b3a71820dff48}, isbn = {978-1-6654-8025-3}, keywords = {dblp}, pages = {1-6}, publisher = {IEEE}, timestamp = {2024-04-09T17:56:11.000+0200}, title = {Hardware-In-the-Loop Simulation of a High Frequency Interleaved Converter based on a Low-Cost FPGA Platform.}, url = {http://dblp.uni-trier.de/db/conf/iecon/iecon2022.html#RobertMCG22}, year = 2022 }