Пожалуйста, войдите в систему, чтобы принять участие в дискуссии (добавить собственные рецензию, или комментарий)
Цитировать эту публикацию
%0 Journal Article
%1 journals/jssc/ShinHPHTSPLJSLS11
%A Shin, Jinuk Luke
%A Huang, Dawei
%A Petrick, Bruce
%A Hwang, Changku
%A Tam, Kenway W.
%A Smith, Alan P.
%A Pham, Ha
%A Li, Hongping Penny
%A Johnson, Timothy
%A Schumacher, Francis
%A Leon, Ana Sonia
%A Strong, Allan
%D 2011
%J IEEE J. Solid State Circuits
%K dblp
%N 1
%P 131-144
%T A 40 nm 16-Core 128-Thread SPARC SoC Processor.
%U http://dblp.uni-trier.de/db/journals/jssc/jssc46.html#ShinHPHTSPLJSLS11
%V 46
@article{journals/jssc/ShinHPHTSPLJSLS11,
added-at = {2021-01-15T00:00:00.000+0100},
author = {Shin, Jinuk Luke and Huang, Dawei and Petrick, Bruce and Hwang, Changku and Tam, Kenway W. and Smith, Alan P. and Pham, Ha and Li, Hongping Penny and Johnson, Timothy and Schumacher, Francis and Leon, Ana Sonia and Strong, Allan},
biburl = {https://www.bibsonomy.org/bibtex/2a361098dc8531717ff9d93cc7e8f67a8/dblp},
ee = {https://doi.org/10.1109/JSSC.2010.2080491},
interhash = {e0328401f82bea420e7e9a092e929c98},
intrahash = {a361098dc8531717ff9d93cc7e8f67a8},
journal = {IEEE J. Solid State Circuits},
keywords = {dblp},
number = 1,
pages = {131-144},
timestamp = {2024-04-08T10:44:44.000+0200},
title = {A 40 nm 16-Core 128-Thread SPARC SoC Processor.},
url = {http://dblp.uni-trier.de/db/journals/jssc/jssc46.html#ShinHPHTSPLJSLS11},
volume = 46,
year = 2011
}