%0 Conference Paper %1 conf/prdc/KitaiOYMM02 %A Kitai, Tomoya %A Oguro, Yusuke %A Yoneda, Tomohiro %A Mercer, Eric %A Myers, Chris J. %B PRDC %D 2002 %I IEEE Computer Society %K dblp %P 210-220 %T Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method. %U http://dblp.uni-trier.de/db/conf/prdc/prdc2002.html#KitaiOYMM02 %@ 0-7695-1852-4

@inproceedings{conf/prdc/KitaiOYMM02, added-at = {2023-03-23T00:00:00.000+0100}, author = {Kitai, Tomoya and Oguro, Yusuke and Yoneda, Tomohiro and Mercer, Eric and Myers, Chris J.}, biburl = {https://www.bibsonomy.org/bibtex/277b7019b65710c0fb1c213e5873c5820/dblp}, booktitle = {PRDC}, crossref = {conf/prdc/2002}, ee = {https://www.wikidata.org/entity/Q59859598}, interhash = {e547a54345ddbf1b98bb0cc3ededfd88}, intrahash = {77b7019b65710c0fb1c213e5873c5820}, isbn = {0-7695-1852-4}, keywords = {dblp}, pages = {210-220}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T09:23:47.000+0200}, title = {Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method.}, url = {http://dblp.uni-trier.de/db/conf/prdc/prdc2002.html#KitaiOYMM02}, year = 2002 }