%0 Journal Article %1 journals/tcad/MahlkeRSSS01 %A Mahlke, Scott A. %A Ravindran, Rajiv A. %A Schlansker, Michael S. %A Schreiber, Robert %A Sherwood, Timothy %D 2001 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 11 %P 1355-1371 %T Bitwidth cognizant architecture synthesis of custom hardwareaccelerators. %U http://dblp.uni-trier.de/db/journals/tcad/tcad20.html#MahlkeRSSS01 %V 20

@article{journals/tcad/MahlkeRSSS01, added-at = {2021-10-14T00:00:00.000+0200}, author = {Mahlke, Scott A. and Ravindran, Rajiv A. and Schlansker, Michael S. and Schreiber, Robert and Sherwood, Timothy}, biburl = {https://www.bibsonomy.org/bibtex/251feb9a2f598fdf6db094ab0e86b831b/dblp}, ee = {https://doi.org/10.1109/43.959864}, interhash = {e761f831c7cec6c336f92449c55755d6}, intrahash = {51feb9a2f598fdf6db094ab0e86b831b}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 11, pages = {1355-1371}, timestamp = {2024-04-08T19:47:00.000+0200}, title = {Bitwidth cognizant architecture synthesis of custom hardwareaccelerators.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad20.html#MahlkeRSSS01}, volume = 20, year = 2001 }