%0 Journal Article %1 journals/jcsc/SharmaRR18 %A Sharma, Rajneesh %A Rathore, Rituraj S. %A Rana, Ashwani K. %D 2018 %J J. Circuits Syst. Comput. %K dblp %N 4 %P 1850063:1-1850063:13 %T Impact of High-k Spacer on Device Performance of Nanoscale Underlap Fully Depleted SOI MOSFET. %U http://dblp.uni-trier.de/db/journals/jcsc/jcsc27.html#SharmaRR18 %V 27

@article{journals/jcsc/SharmaRR18, added-at = {2023-09-30T00:00:00.000+0200}, author = {Sharma, Rajneesh and Rathore, Rituraj S. and Rana, Ashwani K.}, biburl = {https://www.bibsonomy.org/bibtex/20b56e84aa6cb6f586d1f87f928413856/dblp}, ee = {https://doi.org/10.1142/S0218126618500639}, interhash = {e9129f6df4d9eabe06045c72805b62f9}, intrahash = {0b56e84aa6cb6f586d1f87f928413856}, journal = {J. Circuits Syst. Comput.}, keywords = {dblp}, number = 4, pages = {1850063:1-1850063:13}, timestamp = {2024-04-08T19:36:09.000+0200}, title = {Impact of High-k Spacer on Device Performance of Nanoscale Underlap Fully Depleted SOI MOSFET.}, url = {http://dblp.uni-trier.de/db/journals/jcsc/jcsc27.html#SharmaRR18}, volume = 27, year = 2018 }