A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory Cell Design with a Differential Cell Architecture in a Pure CMOS Logic Process for a System LSI.
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%0 Journal Article
%1 journals/ieicet/YamamotoSKNSAKY07
%A Yamamoto, Yasue
%A Shirahama, Masanori
%A Kawasaki, Toshiaki
%A Nishihara, Ryuji
%A Sumi, Shinichi
%A Agata, Yasuhiro
%A Kikukawa, Hirohito
%A Yamauchi, Hiroyuki
%D 2007
%J IEICE Trans. Electron.
%K dblp
%N 5
%P 1129-1137
%T A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory Cell Design with a Differential Cell Architecture in a Pure CMOS Logic Process for a System LSI.
%U http://dblp.uni-trier.de/db/journals/ieicet/ieicet90c.html#YamamotoSKNSAKY07
%V 90-C
@article{journals/ieicet/YamamotoSKNSAKY07,
added-at = {2024-02-05T00:00:00.000+0100},
author = {Yamamoto, Yasue and Shirahama, Masanori and Kawasaki, Toshiaki and Nishihara, Ryuji and Sumi, Shinichi and Agata, Yasuhiro and Kikukawa, Hirohito and Yamauchi, Hiroyuki},
biburl = {https://www.bibsonomy.org/bibtex/219c808935da97535f36c63e7eab676f8/dblp},
ee = {https://doi.org/10.1093/ietele/e90-c.5.1129},
interhash = {ede48443a952d8ae480314f2e6dacb9f},
intrahash = {19c808935da97535f36c63e7eab676f8},
journal = {IEICE Trans. Electron.},
keywords = {dblp},
number = 5,
pages = {1129-1137},
timestamp = {2024-04-08T15:48:38.000+0200},
title = {A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory Cell Design with a Differential Cell Architecture in a Pure CMOS Logic Process for a System LSI.},
url = {http://dblp.uni-trier.de/db/journals/ieicet/ieicet90c.html#YamamotoSKNSAKY07},
volume = {90-C},
year = 2007
}
