%0 Journal Article %1 journals/tcad/ZhuD96 %A Zhu, Qing %A Dai, Wayne Wei-Ming %D 1996 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 9 %P 1106-1118 %T High-speed clock network sizing optimization based on distributed RC and lossy RLC interconnect models. %U http://dblp.uni-trier.de/db/journals/tcad/tcad15.html#ZhuD96 %V 15

@article{journals/tcad/ZhuD96, added-at = {2020-09-24T00:00:00.000+0200}, author = {Zhu, Qing and Dai, Wayne Wei-Ming}, biburl = {https://www.bibsonomy.org/bibtex/221edcdab6764033cd5304cc598c7f99b/dblp}, ee = {https://doi.org/10.1109/43.536716}, interhash = {f165112cd5ad774829231a6f062a9c2a}, intrahash = {21edcdab6764033cd5304cc598c7f99b}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 9, pages = {1106-1118}, timestamp = {2020-09-25T11:48:57.000+0200}, title = {High-speed clock network sizing optimization based on distributed RC and lossy RLC interconnect models.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad15.html#ZhuD96}, volume = 15, year = 1996 }