%0 Journal Article %1 journals/iet-cds/MandalMB14 %A Mandal, Debashis %A Mandal, Pradip %A Bhattacharyya, T. K. %D 2014 %J IET Circuits Devices Syst. %K dblp %N 4 %P 237-245 %T Spur reducing architecture of frequency synthesiser using switched capacitors. %U http://dblp.uni-trier.de/db/journals/iet-cds/iet-cds8.html#MandalMB14 %V 8

@article{journals/iet-cds/MandalMB14, added-at = {2020-09-10T00:00:00.000+0200}, author = {Mandal, Debashis and Mandal, Pradip and Bhattacharyya, T. K.}, biburl = {https://www.bibsonomy.org/bibtex/255c491cc3d748f6424607ed4304782da/dblp}, ee = {https://doi.org/10.1049/iet-cds.2013.0200}, interhash = {f2de8fe4a4c27228f364aa73476a96d4}, intrahash = {55c491cc3d748f6424607ed4304782da}, journal = {IET Circuits Devices Syst.}, keywords = {dblp}, number = 4, pages = {237-245}, timestamp = {2020-09-11T11:44:35.000+0200}, title = {Spur reducing architecture of frequency synthesiser using switched capacitors.}, url = {http://dblp.uni-trier.de/db/journals/iet-cds/iet-cds8.html#MandalMB14}, volume = 8, year = 2014 }