%0 Journal Article %1 journals/tcasI/ZhangHDXL22 %A Zhang, Zhijun %A He, Haotian %A Deng, Xianzhi %A Xie, Jilong %A Luo, Yamei %D 2022 %J IEEE Trans. Circuits Syst. I Regul. Pap. %K dblp %N 6 %P 2502-2515 %T FPGA-Type Configurable Coprocessor Implementation Scheme of Recurrent Neural Network for Solving Time-Varying QP Problems. %U http://dblp.uni-trier.de/db/journals/tcasI/tcasI69.html#ZhangHDXL22 %V 69

@article{journals/tcasI/ZhangHDXL22, added-at = {2022-10-02T00:00:00.000+0200}, author = {Zhang, Zhijun and He, Haotian and Deng, Xianzhi and Xie, Jilong and Luo, Yamei}, biburl = {https://www.bibsonomy.org/bibtex/21c9290b81b3dfc98cc2e43e4aa22b48f/dblp}, ee = {https://doi.org/10.1109/TCSI.2022.3153560}, interhash = {f8e973fbea8c97d18f918712a123a13d}, intrahash = {1c9290b81b3dfc98cc2e43e4aa22b48f}, journal = {IEEE Trans. Circuits Syst. I Regul. Pap.}, keywords = {dblp}, number = 6, pages = {2502-2515}, timestamp = {2024-04-08T16:47:57.000+0200}, title = {FPGA-Type Configurable Coprocessor Implementation Scheme of Recurrent Neural Network for Solving Time-Varying QP Problems.}, url = {http://dblp.uni-trier.de/db/journals/tcasI/tcasI69.html#ZhangHDXL22}, volume = 69, year = 2022 }