%0 Journal Article %1 journals/jssc/HsuAS20 %A Hsu, Chen-Kai %A Andeen, Timothy R. %A Sun, Nan %D 2020 %J IEEE J. Solid State Circuits %K dblp %N 4 %P 1032-1042 %T A Pipeline SAR ADC With Second-Order Interstage Gain Error Shaping. %U http://dblp.uni-trier.de/db/journals/jssc/jssc55.html#HsuAS20 %V 55

@article{journals/jssc/HsuAS20, added-at = {2023-09-25T00:00:00.000+0200}, author = {Hsu, Chen-Kai and Andeen, Timothy R. and Sun, Nan}, biburl = {https://www.bibsonomy.org/bibtex/2f1db57fc1102ebec3dcade336b0bb134/dblp}, ee = {https://doi.org/10.1109/JSSC.2019.2962140}, interhash = {fbfe624506fab4069be7268823cc6fd5}, intrahash = {f1db57fc1102ebec3dcade336b0bb134}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 4, pages = {1032-1042}, timestamp = {2024-04-08T10:43:40.000+0200}, title = {A Pipeline SAR ADC With Second-Order Interstage Gain Error Shaping.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc55.html#HsuAS20}, volume = 55, year = 2020 }