%0 Conference Paper %1 conf/vlsid/NowickJC95 %A Nowick, Steven M. %A Jha, Niraj K. %A Cheng, Fu-Chiung %B VLSI Design %D 1995 %I IEEE Computer Society %K dblp %P 171-176 %T Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid1995.html#NowickJC95 %@ 0-8186-6905-5

@inproceedings{conf/vlsid/NowickJC95, added-at = {2023-03-24T00:00:00.000+0100}, author = {Nowick, Steven M. and Jha, Niraj K. and Cheng, Fu-Chiung}, biburl = {https://www.bibsonomy.org/bibtex/2048196651bfbd72060f7be49656a87c8/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/1995}, ee = {https://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512099}, interhash = {fc37c921d7b864093b6f4ec6d74069e7}, intrahash = {048196651bfbd72060f7be49656a87c8}, isbn = {0-8186-6905-5}, keywords = {dblp}, pages = {171-176}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T05:46:44.000+0200}, title = {Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid1995.html#NowickJC95}, year = 1995 }