%0 Conference Paper %1 conf/vlsid/TsaiBCS05 %A Tsai, Jeng-Liang %A Baik, Dong Hyun %A Chen, Charlie Chung-Ping %A Saluja, Kewal K. %B VLSI Design %D 2005 %I IEEE Computer Society %K dblp %P 423-426 %T False Path and Clock Scheduling Based Yield-Aware Gate Sizing. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2005.html#TsaiBCS05 %@ 0-7695-2264-5

@inproceedings{conf/vlsid/TsaiBCS05, added-at = {2023-03-24T00:00:00.000+0100}, author = {Tsai, Jeng-Liang and Baik, Dong Hyun and Chen, Charlie Chung-Ping and Saluja, Kewal K.}, biburl = {https://www.bibsonomy.org/bibtex/2109dbc44abf1612a852b80910b926dd7/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2005}, ee = {https://doi.ieeecomputersociety.org/10.1109/ICVD.2005.99}, interhash = {502e13ba2072a477a2e54955462d046d}, intrahash = {109dbc44abf1612a852b80910b926dd7}, isbn = {0-7695-2264-5}, keywords = {dblp}, pages = {423-426}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:18:41.000+0200}, title = {False Path and Clock Scheduling Based Yield-Aware Gate Sizing.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2005.html#TsaiBCS05}, year = 2005 }