%0 Conference Paper %1 conf/dac/PomeranzR01 %A Pomeranz, Irith %A Reddy, Sudhakar M. %B DAC %D 2001 %I ACM %K dblp %P 156-161 %T An Approach to Test Compaction for Scan Circuits that Enhances At-Speed Testing. %U http://dblp.uni-trier.de/db/conf/dac/dac2001.html#PomeranzR01 %@ 1-58113-297-2

@inproceedings{conf/dac/PomeranzR01, added-at = {2018-11-06T00:00:00.000+0100}, author = {Pomeranz, Irith and Reddy, Sudhakar M.}, biburl = {https://www.bibsonomy.org/bibtex/21ad9cf0d192278ad514245a18205b72b/dblp}, booktitle = {DAC}, crossref = {conf/dac/2001}, ee = {https://doi.org/10.1145/378239.378390}, interhash = {51189276584e00ac389e6558ce26172f}, intrahash = {1ad9cf0d192278ad514245a18205b72b}, isbn = {1-58113-297-2}, keywords = {dblp}, pages = {156-161}, publisher = {ACM}, timestamp = {2018-11-07T15:12:46.000+0100}, title = {An Approach to Test Compaction for Scan Circuits that Enhances At-Speed Testing.}, url = {http://dblp.uni-trier.de/db/conf/dac/dac2001.html#PomeranzR01}, year = 2001 }