%0 Conference Paper %1 conf/isscc/TeradaONKKY09 %A Terada, Jun %A Ohtomo, Yusuke %A Nishimura, Kazuyoshi %A Katsurai, Hiroaki %A Kimura, Shunji %A Yoshimoto, Naoto %B ISSCC %D 2009 %I IEEE %K dblp %P 104-105 %T Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit. %U http://dblp.uni-trier.de/db/conf/isscc/isscc2009.html#TeradaONKKY09 %@ 978-1-4244-3458-9

@inproceedings{conf/isscc/TeradaONKKY09, added-at = {2018-11-02T00:00:00.000+0100}, author = {Terada, Jun and Ohtomo, Yusuke and Nishimura, Kazuyoshi and Katsurai, Hiroaki and Kimura, Shunji and Yoshimoto, Naoto}, biburl = {https://www.bibsonomy.org/bibtex/21b67e883134f8baaf1d8d473cf91cd5f/dblp}, booktitle = {ISSCC}, crossref = {conf/isscc/2009}, ee = {https://doi.org/10.1109/ISSCC.2009.4977329}, interhash = {25a6dafb1cc4750a463d3929c65f51fe}, intrahash = {1b67e883134f8baaf1d8d473cf91cd5f}, isbn = {978-1-4244-3458-9}, keywords = {dblp}, pages = {104-105}, publisher = {IEEE}, timestamp = {2018-11-03T16:40:39.000+0100}, title = {Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit.}, url = {http://dblp.uni-trier.de/db/conf/isscc/isscc2009.html#TeradaONKKY09}, year = 2009 }