%0 Journal Article %1 journals/ieicet/HariyamaSK05 %A Hariyama, Masanori %A Sasaki, Haruka %A Kameyama, Michitaka %D 2005 %J IEICE Trans. Inf. Syst. %K dblp %N 7 %P 1486-1491 %T Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access. %U http://dblp.uni-trier.de/db/journals/ieicet/ieicet88d.html#HariyamaSK05 %V 88-D

@article{journals/ieicet/HariyamaSK05, added-at = {2020-04-11T00:00:00.000+0200}, author = {Hariyama, Masanori and Sasaki, Haruka and Kameyama, Michitaka}, biburl = {https://www.bibsonomy.org/bibtex/224eb6833e1ce5df69b6890f3292a2f79/dblp}, ee = {https://doi.org/10.1093/ietisy/e88-d.7.1486}, interhash = {9275d4f679c77f4ad176f0c48c88649a}, intrahash = {24eb6833e1ce5df69b6890f3292a2f79}, journal = {IEICE Trans. Inf. Syst.}, keywords = {dblp}, number = 7, pages = {1486-1491}, timestamp = {2020-04-14T12:01:10.000+0200}, title = {Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access.}, url = {http://dblp.uni-trier.de/db/journals/ieicet/ieicet88d.html#HariyamaSK05}, volume = {88-D}, year = 2005 }