%0 Conference Paper %1 conf/esscirc/MadeiraLH07 %A Madeira, Paul %A LaCroix, Marc-Andre %A Hogeboom, John %B ESSCIRC %D 2007 %E Schmitt-Landsiedel, Doris %E Noll, Tobias %I IEEE %K dblp %P 532-535 %T A low jitter clocking strategy for a 7.5-Gb/s SerDes array in 65nm CMOS technology. %U http://dblp.uni-trier.de/db/conf/esscirc/esscirc2007.html#MadeiraLH07 %@ 978-1-4244-1125-2

@inproceedings{conf/esscirc/MadeiraLH07, added-at = {2021-10-18T00:00:00.000+0200}, author = {Madeira, Paul and LaCroix, Marc-Andre and Hogeboom, John}, biburl = {https://www.bibsonomy.org/bibtex/22d0b64b496cc6511314d258de114dcc4/dblp}, booktitle = {ESSCIRC}, crossref = {conf/esscirc/2007}, editor = {Schmitt-Landsiedel, Doris and Noll, Tobias}, ee = {https://doi.org/10.1109/ESSCIRC.2007.4430359}, interhash = {bc3de118f3f8a6992114253eca2145f0}, intrahash = {2d0b64b496cc6511314d258de114dcc4}, isbn = {978-1-4244-1125-2}, keywords = {dblp}, pages = {532-535}, publisher = {IEEE}, timestamp = {2024-04-09T17:24:52.000+0200}, title = {A low jitter clocking strategy for a 7.5-Gb/s SerDes array in 65nm CMOS technology.}, url = {http://dblp.uni-trier.de/db/conf/esscirc/esscirc2007.html#MadeiraLH07}, year = 2007 }