%0 Conference Paper %1 conf/vlsid/PatelSMN04 %A Patel, Nirav %A Srihari, M. %A Maheswari, Pooja %A Nandakumar, G. N. %B VLSI Design %D 2004 %I IEEE Computer Society %K dblp %P 769-772 %T An Efficient Method to Generate Test Vectors for Combinational Cell Verification. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2004.html#PatelSMN04 %@ 0-7695-2072-3

@inproceedings{conf/vlsid/PatelSMN04, added-at = {2023-03-24T00:00:00.000+0100}, author = {Patel, Nirav and Srihari, M. and Maheswari, Pooja and Nandakumar, G. N.}, biburl = {https://www.bibsonomy.org/bibtex/22df0535f322e0220cd9d18e40adb1d03/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2004}, ee = {https://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1261023}, interhash = {6c9f4a19c52ef266ec36431b9742a3bb}, intrahash = {2df0535f322e0220cd9d18e40adb1d03}, isbn = {0-7695-2072-3}, keywords = {dblp}, pages = {769-772}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:18:22.000+0200}, title = {An Efficient Method to Generate Test Vectors for Combinational Cell Verification.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2004.html#PatelSMN04}, year = 2004 }