%0 Conference Paper %1 conf/vlsid/HeraguPA96 %A Heragu, Keerthi %A Patel, Janak H. %A Agrawal, Vishwani D. %B VLSI Design %D 1996 %I IEEE Computer Society %K dblp %P 422-425 %T Improving accuracy in path delay fault coverage estimation. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid1996.html#HeraguPA96 %@ 0-8186-7228-5

@inproceedings{conf/vlsid/HeraguPA96, added-at = {2023-03-24T00:00:00.000+0100}, author = {Heragu, Keerthi and Patel, Janak H. and Agrawal, Vishwani D.}, biburl = {https://www.bibsonomy.org/bibtex/22ee829ef9cb230d4c2d4fd7240332267/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/1996}, ee = {https://doi.ieeecomputersociety.org/10.1109/ICVD.1996.489646}, interhash = {b1f0f2b71c1d00bca04d781967a7ee68}, intrahash = {2ee829ef9cb230d4c2d4fd7240332267}, isbn = {0-8186-7228-5}, keywords = {dblp}, pages = {422-425}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T05:46:51.000+0200}, title = {Improving accuracy in path delay fault coverage estimation.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid1996.html#HeraguPA96}, year = 1996 }