%0 Conference Paper %1 conf/dac/IyengarG14 %A Iyengar, Anirudh %A Ghosh, Swaroop %B DAC %D 2014 %I ACM %K dblp %P 65:1-65:6 %T Modeling and Analysis of Domain Wall Dynamics for Robust and Low-Power Embedded Memory. %U http://dblp.uni-trier.de/db/conf/dac/dac2014.html#IyengarG14 %@ 978-1-4503-2730-5

@inproceedings{conf/dac/IyengarG14, added-at = {2018-11-06T00:00:00.000+0100}, author = {Iyengar, Anirudh and Ghosh, Swaroop}, biburl = {https://www.bibsonomy.org/bibtex/22f7d20af8748217dd59e8350f515ce2d/dblp}, booktitle = {DAC}, crossref = {conf/dac/2014}, ee = {https://doi.org/10.1145/2593069.2593161}, interhash = {d91166d65b3cf5d64c36376dd510d313}, intrahash = {2f7d20af8748217dd59e8350f515ce2d}, isbn = {978-1-4503-2730-5}, keywords = {dblp}, pages = {65:1-65:6}, publisher = {ACM}, timestamp = {2018-11-07T15:14:38.000+0100}, title = {Modeling and Analysis of Domain Wall Dynamics for Robust and Low-Power Embedded Memory.}, url = {http://dblp.uni-trier.de/db/conf/dac/dac2014.html#IyengarG14}, year = 2014 }