To improve noise tolerance of link transmission and router buffers, we propose an error control scheme that integrates a powerful link error recovery method, an efficient buffer error correction coding, and an algorithm to further manage the loss of header and tail flits in a packet. With this method, header and tail flits can be effectively protected, reducing network saturation. Simulation results show the proposed scheme achieves up to a 9x improvement in operation time before saturation and 26% higher throughput than other error control methods. Simulations performed on a parallel FFT application mapped on a 4×4 mesh NoC demonstrate that the proposed error control scheme reduces the total computation time over a previous method in the high noise region.
Beschreibung
IEEE Xplore - Error control integration scheme for reliable NoC
%0 Conference Paper
%1 yu2010reliable
%A Yu, Qiaoyan
%A Zhang, Bo
%A Li, Yan
%A Ampadu, P.
%B Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
%D 2010
%K noc reliability
%P 3893-3896
%R 10.1109/ISCAS.2010.5537694
%T Error control integration scheme for reliable NoC
%U http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=5537694&navigation=1
%X To improve noise tolerance of link transmission and router buffers, we propose an error control scheme that integrates a powerful link error recovery method, an efficient buffer error correction coding, and an algorithm to further manage the loss of header and tail flits in a packet. With this method, header and tail flits can be effectively protected, reducing network saturation. Simulation results show the proposed scheme achieves up to a 9x improvement in operation time before saturation and 26% higher throughput than other error control methods. Simulations performed on a parallel FFT application mapped on a 4×4 mesh NoC demonstrate that the proposed error control scheme reduces the total computation time over a previous method in the high noise region.
@inproceedings{yu2010reliable,
abstract = {To improve noise tolerance of link transmission and router buffers, we propose an error control scheme that integrates a powerful link error recovery method, an efficient buffer error correction coding, and an algorithm to further manage the loss of header and tail flits in a packet. With this method, header and tail flits can be effectively protected, reducing network saturation. Simulation results show the proposed scheme achieves up to a 9x improvement in operation time before saturation and 26% higher throughput than other error control methods. Simulations performed on a parallel FFT application mapped on a 4×4 mesh NoC demonstrate that the proposed error control scheme reduces the total computation time over a previous method in the high noise region.},
added-at = {2013-04-17T16:31:10.000+0200},
author = {Yu, Qiaoyan and Zhang, Bo and Li, Yan and Ampadu, P.},
biburl = {https://www.bibsonomy.org/bibtex/2322a99fca68fc108fd0891cd61d97cc2/eberle18},
booktitle = {Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on},
description = {IEEE Xplore - Error control integration scheme for reliable NoC},
doi = {10.1109/ISCAS.2010.5537694},
interhash = {58423a718d883a18a48e8e4ee3fc4699},
intrahash = {322a99fca68fc108fd0891cd61d97cc2},
keywords = {noc reliability},
pages = {3893-3896},
timestamp = {2013-04-17T16:31:10.000+0200},
title = {Error control integration scheme for reliable NoC},
url = {http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=5537694&navigation=1},
year = 2010
}