%0 Conference Paper %1 conf/isvlsi/WilleSSD12 %A Wille, Robert %A Soeken, Mathias %A Schönborn, Eleonora %A Drechsler, Rolf %B ISVLSI %D 2012 %I IEEE Computer Society %K dblp %P 213-218 %T Circuit Line Minimization in the HDL-Based Synthesis of Reversible Logic. %U http://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2012.html#WilleSSD12 %@ 978-1-4673-2234-8

@inproceedings{conf/isvlsi/WilleSSD12, added-at = {2023-03-24T00:00:00.000+0100}, author = {Wille, Robert and Soeken, Mathias and Schönborn, Eleonora and Drechsler, Rolf}, biburl = {https://www.bibsonomy.org/bibtex/237dd50b6aa6664b5ab1915a56f9f9ec4/dblp}, booktitle = {ISVLSI}, crossref = {conf/isvlsi/2012}, ee = {https://www.wikidata.org/entity/Q59242452}, interhash = {b735bc9fc7fb4d7df25b1b8a991fde1f}, intrahash = {37dd50b6aa6664b5ab1915a56f9f9ec4}, isbn = {978-1-4673-2234-8}, keywords = {dblp}, pages = {213-218}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T11:07:47.000+0200}, title = {Circuit Line Minimization in the HDL-Based Synthesis of Reversible Logic.}, url = {http://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2012.html#WilleSSD12}, year = 2012 }