%0 Conference Paper %1 conf/arith/HormigoC21 %A Hormigo, Javier %A Caffarena, Gabriel %B ARITH %D 2021 %I IEEE %K dblp %P 119-122 %T FPGA acceleration of bit-true simulations for word-length optimization. %U http://dblp.uni-trier.de/db/conf/arith/arith2021.html#HormigoC21 %@ 978-1-6654-2293-2

@inproceedings{conf/arith/HormigoC21, added-at = {2021-11-23T00:00:00.000+0100}, author = {Hormigo, Javier and Caffarena, Gabriel}, biburl = {https://www.bibsonomy.org/bibtex/23db50489398ed7b5ef2a6b7d078bf6b6/dblp}, booktitle = {ARITH}, crossref = {conf/arith/2021}, ee = {https://doi.org/10.1109/ARITH51176.2021.00033}, interhash = {e4f814896afa9363503f2518c0399519}, intrahash = {3db50489398ed7b5ef2a6b7d078bf6b6}, isbn = {978-1-6654-2293-2}, keywords = {dblp}, pages = {119-122}, publisher = {IEEE}, timestamp = {2024-04-09T16:06:58.000+0200}, title = {FPGA acceleration of bit-true simulations for word-length optimization.}, url = {http://dblp.uni-trier.de/db/conf/arith/arith2021.html#HormigoC21}, year = 2021 }