%0 Journal Article %1 noauthororeditor %A Sahari, Muhammad Sadiq %A A’ain, Abu Khari %A Grout, Ian A. %D 2015 %E Kumar, Dr. Shiv %J International Journal of Innovative Science and Modern Engineering (IJISME) %K (BIST) (IC) (TPG) Antirandom Built-in Circuit Generation Integrated Pattern Pseudorandom Test Testing Testing. and self-test %N 4 %P 33-35 %T Scalable Antirandom Testing (SAT) %U https://www.ijisme.org/wp-content/uploads/papers/v3i4/D0820033415.pdf %V 3 %X Antirandom testing approach requires large input space and complex test vector generation algorithm when used on circuit under test (CUT) with large number of inputs. In this work, we proposed a novel and simple approach of Antirandom sequence generation by using the least significant bit (LSB) of the test vector as a reference to generate the next test vector. Fault simulations on ISCAS’85 benchmark circuits shown that a high fault coverage for combinational logic circuits has been obtained. Another attractive feature of the proposed technique is the scalable of the algorithm that can be generate test vectors in short time even for CUT with large number of inputs.

@article{noauthororeditor, abstract = {Antirandom testing approach requires large input space and complex test vector generation algorithm when used on circuit under test (CUT) with large number of inputs. In this work, we proposed a novel and simple approach of Antirandom sequence generation by using the least significant bit (LSB) of the test vector as a reference to generate the next test vector. Fault simulations on ISCAS’85 benchmark circuits shown that a high fault coverage for combinational logic circuits has been obtained. Another attractive feature of the proposed technique is the scalable of the algorithm that can be generate test vectors in short time even for CUT with large number of inputs.}, added-at = {2021-09-20T13:50:58.000+0200}, author = {Sahari, Muhammad Sadiq and A’ain, Abu Khari and Grout, Ian A.}, biburl = {https://www.bibsonomy.org/bibtex/2456c411dbded492920ca97c4ced51c18/ijisme_beiesp}, editor = {Kumar, Dr. Shiv}, interhash = {7839ed6cf2c991476351f318586ffeb7}, intrahash = {456c411dbded492920ca97c4ced51c18}, issn = {2319-6386}, journal = {International Journal of Innovative Science and Modern Engineering (IJISME)}, keywords = {(BIST) (IC) (TPG) Antirandom Built-in Circuit Generation Integrated Pattern Pseudorandom Test Testing Testing. and self-test}, language = {En}, month = {March}, number = 4, pages = {33-35}, timestamp = {2021-09-20T13:50:58.000+0200}, title = {Scalable Antirandom Testing (SAT)}, url = {https://www.ijisme.org/wp-content/uploads/papers/v3i4/D0820033415.pdf}, volume = 3, year = 2015 }