%0 Journal Article %1 journals/jssc/NuytsSDRD12 %A Nuyts, Pieter A. J. %A Singerl, Peter %A Dielacher, Franz %A Reynaert, Patrick %A Dehaene, Wim %D 2012 %J IEEE J. Solid State Circuits %K dblp %N 7 %P 1681-1692 %T A Fully Digital Delay Line Based GHz Range Multimode Transmitter Front-End in 65-nm CMOS. %U http://dblp.uni-trier.de/db/journals/jssc/jssc47.html#NuytsSDRD12 %V 47

@article{journals/jssc/NuytsSDRD12, added-at = {2021-10-14T00:00:00.000+0200}, author = {Nuyts, Pieter A. J. and Singerl, Peter and Dielacher, Franz and Reynaert, Patrick and Dehaene, Wim}, biburl = {https://www.bibsonomy.org/bibtex/248deb29c42d014b3ceb024457c2cd0c8/dblp}, ee = {https://doi.org/10.1109/JSSC.2012.2191032}, interhash = {34ea940a8a266f745861c94a1ba562c1}, intrahash = {48deb29c42d014b3ceb024457c2cd0c8}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 7, pages = {1681-1692}, timestamp = {2024-04-08T10:43:19.000+0200}, title = {A Fully Digital Delay Line Based GHz Range Multimode Transmitter Front-End in 65-nm CMOS.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc47.html#NuytsSDRD12}, volume = 47, year = 2012 }