%0 Conference Paper %1 conf/essderc/LarrieuGHC15 %A Larrieu, G. %A Guerfi, Y. %A Han, X. L. %A Clement, N. %B ESSDERC %D 2015 %I IEEE %K dblp %P 202-205 %T Vertical field effect transistor with sub-15nm gate-all-around on Si nanowire array. %U http://dblp.uni-trier.de/db/conf/essderc/essderc2015.html#LarrieuGHC15 %@ 978-1-4673-7135-3

@inproceedings{conf/essderc/LarrieuGHC15, added-at = {2017-05-19T00:00:00.000+0200}, author = {Larrieu, G. and Guerfi, Y. and Han, X. L. and Clement, N.}, biburl = {https://www.bibsonomy.org/bibtex/2497f1dc3bbb0f90c209f1a8e809bd274/dblp}, booktitle = {ESSDERC}, crossref = {conf/essderc/2015}, ee = {https://doi.org/10.1109/ESSDERC.2015.7324750}, interhash = {c97793be5301fa7093711a3733c3b5ec}, intrahash = {497f1dc3bbb0f90c209f1a8e809bd274}, isbn = {978-1-4673-7135-3}, keywords = {dblp}, pages = {202-205}, publisher = {IEEE}, timestamp = {2019-10-17T12:39:51.000+0200}, title = {Vertical field effect transistor with sub-15nm gate-all-around on Si nanowire array.}, url = {http://dblp.uni-trier.de/db/conf/essderc/essderc2015.html#LarrieuGHC15}, year = 2015 }