%0 Journal Article %1 journals/tvlsi/FengL17 %A Feng, Xiang %A Li, Shuguo %D 2017 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 9 %P 2658-2662 %T Design of an Area-Effcient Million-Bit Integer Multiplier Using Double Modulus NTT. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi25.html#FengL17 %V 25

@article{journals/tvlsi/FengL17, added-at = {2020-03-11T00:00:00.000+0100}, author = {Feng, Xiang and Li, Shuguo}, biburl = {https://www.bibsonomy.org/bibtex/24986919f27874f0690811031e5078273/dblp}, ee = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2017.2691727}, interhash = {256bea018698291665918d630ece644d}, intrahash = {4986919f27874f0690811031e5078273}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 9, pages = {2658-2662}, timestamp = {2020-03-12T11:44:55.000+0100}, title = {Design of an Area-Effcient Million-Bit Integer Multiplier Using Double Modulus NTT.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi25.html#FengL17}, volume = 25, year = 2017 }