%0 Conference Paper %1 conf/ismvl/NakajimaK96 %A Nakajima, Masami %A Kameyama, Michitaka %B ISMVL %D 1996 %I IEEE Computer Society %K dblp %P 104-109 %T Design of Highly Parallel Linear Digital Circuits Based on Symbol-Level Redundancy. %U http://dblp.uni-trier.de/db/conf/ismvl/ismvl1996.html#NakajimaK96 %@ 0-8186-7392-3

@inproceedings{conf/ismvl/NakajimaK96, added-at = {2023-03-23T00:00:00.000+0100}, author = {Nakajima, Masami and Kameyama, Michitaka}, biburl = {https://www.bibsonomy.org/bibtex/25583184e778b074d68c0b7e3b53d10f3/dblp}, booktitle = {ISMVL}, crossref = {conf/ismvl/1996}, ee = {https://doi.ieeecomputersociety.org/10.1109/ISMVL.1996.508344}, interhash = {095f9af540e99760c6c5b3a60da04317}, intrahash = {5583184e778b074d68c0b7e3b53d10f3}, isbn = {0-8186-7392-3}, keywords = {dblp}, pages = {104-109}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T15:37:15.000+0200}, title = {Design of Highly Parallel Linear Digital Circuits Based on Symbol-Level Redundancy.}, url = {http://dblp.uni-trier.de/db/conf/ismvl/ismvl1996.html#NakajimaK96}, year = 1996 }