%0 Conference Paper %1 conf/fpl/SaundersF06 %A Saunders, Paul %A Fagan, Anthony D. %B FPL %D 2006 %I IEEE %K dblp %P 1-6 %T A High Speed, Low Memory FPGA Based LDPC Decoder Architecture for Quasi-Cyclic LDPC Codes. %U http://dblp.uni-trier.de/db/conf/fpl/fpl2006.html#SaundersF06 %@ 1-4244-0312-X

@inproceedings{conf/fpl/SaundersF06, added-at = {2017-05-21T00:00:00.000+0200}, author = {Saunders, Paul and Fagan, Anthony D.}, biburl = {https://www.bibsonomy.org/bibtex/25ad3b43c8465ad13a30d77ed18218217/dblp}, booktitle = {FPL}, crossref = {conf/fpl/2006}, ee = {https://doi.org/10.1109/FPL.2006.311328}, interhash = {c4a681ff15b65329d7d3b6ef12f676f2}, intrahash = {5ad3b43c8465ad13a30d77ed18218217}, isbn = {1-4244-0312-X}, keywords = {dblp}, pages = {1-6}, publisher = {IEEE}, timestamp = {2019-10-17T19:14:15.000+0200}, title = {A High Speed, Low Memory FPGA Based LDPC Decoder Architecture for Quasi-Cyclic LDPC Codes.}, url = {http://dblp.uni-trier.de/db/conf/fpl/fpl2006.html#SaundersF06}, year = 2006 }