%0 Journal Article %1 journals/tpds/SihL93 %A Sih, Gilbert C. %A Lee, Edward A. %D 1993 %J IEEE Trans. Parallel Distributed Syst. %K dblp %N 2 %P 175-187 %T A Compile-Time Scheduling Heuristic for Interconnection-Constrained Heterogeneous Processor Architectures. %U http://dblp.uni-trier.de/db/journals/tpds/tpds4.html#SihL93 %V 4

@article{journals/tpds/SihL93, added-at = {2020-10-02T00:00:00.000+0200}, author = {Sih, Gilbert C. and Lee, Edward A.}, biburl = {https://www.bibsonomy.org/bibtex/25caccd53ff1a8aaffd1b05bcd73de116/dblp}, ee = {http://doi.ieeecomputersociety.org/10.1109/71.207593}, interhash = {af5212b312ef3a911efc7321b2504db8}, intrahash = {5caccd53ff1a8aaffd1b05bcd73de116}, journal = {IEEE Trans. Parallel Distributed Syst.}, keywords = {dblp}, number = 2, pages = {175-187}, timestamp = {2020-10-03T11:38:13.000+0200}, title = {A Compile-Time Scheduling Heuristic for Interconnection-Constrained Heterogeneous Processor Architectures.}, url = {http://dblp.uni-trier.de/db/journals/tpds/tpds4.html#SihL93}, volume = 4, year = 1993 }