%0 Conference Paper %1 conf/vlsi-dat/ChenYLW14 %A Chen, Chia-I %A Yu, Chin-Yeh %A Lu, Yen-Ju %A Wu, Chi-Feng %B VLSI-DAT %D 2014 %I IEEE %K dblp %P 1-4 %T Apply high-level synthesis design and verification methodology on floating-point unit implementation. %U http://dblp.uni-trier.de/db/conf/vlsi-dat/vlsi-dat2014.html#ChenYLW14

@inproceedings{conf/vlsi-dat/ChenYLW14, added-at = {2015-11-12T00:00:00.000+0100}, author = {Chen, Chia-I and Yu, Chin-Yeh and Lu, Yen-Ju and Wu, Chi-Feng}, biburl = {https://www.bibsonomy.org/bibtex/25e284a4912ac7cc9ca02b6e8507dabcd/dblp}, booktitle = {VLSI-DAT}, crossref = {conf/vlsi-dat/2014}, ee = {http://dx.doi.org/10.1109/VLSI-DAT.2014.6834921}, interhash = {9eda345528a148a236482f445b89a6c3}, intrahash = {5e284a4912ac7cc9ca02b6e8507dabcd}, keywords = {dblp}, pages = {1-4}, publisher = {IEEE}, timestamp = {2015-11-13T12:05:44.000+0100}, title = {Apply high-level synthesis design and verification methodology on floating-point unit implementation.}, url = {http://dblp.uni-trier.de/db/conf/vlsi-dat/vlsi-dat2014.html#ChenYLW14}, year = 2014 }