%0 Conference Paper %1 conf/iscas/KakaniDJ04 %A Kakani, Vasanth %A Dai, Foster F. %A Jaeger, Richard C. %B ISCAS (2) %D 2004 %I IEEE %K dblp %P 869-872 %T Delay analysis and optimal biasing for high speed low power Current Mode Logic circuits. %U http://dblp.uni-trier.de/db/conf/iscas/iscas2004-2.html#KakaniDJ04 %@ 0-7803-8251-X

@inproceedings{conf/iscas/KakaniDJ04, added-at = {2016-05-20T00:00:00.000+0200}, author = {Kakani, Vasanth and Dai, Foster F. and Jaeger, Richard C.}, biburl = {https://www.bibsonomy.org/bibtex/2621f96be76130f38a000350bdeb8db39/dblp}, booktitle = {ISCAS (2)}, crossref = {conf/iscas/2004}, ee = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=9255}, interhash = {05d1ce2b580d979453db2d2837286976}, intrahash = {621f96be76130f38a000350bdeb8db39}, isbn = {0-7803-8251-X}, keywords = {dblp}, pages = {869-872}, publisher = {IEEE}, timestamp = {2016-05-21T12:25:01.000+0200}, title = {Delay analysis and optimal biasing for high speed low power Current Mode Logic circuits.}, url = {http://dblp.uni-trier.de/db/conf/iscas/iscas2004-2.html#KakaniDJ04}, year = 2004 }