%0 Conference Paper %1 conf/aspdac/ChenXWT10 %A Chen, Yibo %A Xie, Yuan %A Wang, Yu %A Takach, Andrés %B ASP-DAC %D 2010 %I IEEE %K dblp %P 689-694 %T Minimizing leakage power in aging-bounded high-level synthesis with design time multi-Vth assignment. %U http://dblp.uni-trier.de/db/conf/aspdac/aspdac2010.html#ChenXWT10 %@ 978-1-60558-837-7

@inproceedings{conf/aspdac/ChenXWT10, added-at = {2017-06-01T00:00:00.000+0200}, author = {Chen, Yibo and Xie, Yuan and Wang, Yu and Takach, Andrés}, biburl = {https://www.bibsonomy.org/bibtex/264999648cce3bbfbf430f299751321d9/dblp}, booktitle = {ASP-DAC}, crossref = {conf/aspdac/2010}, ee = {http://dl.acm.org/citation.cfm?id=1899882}, interhash = {597c60a0c7560817e71bfc603ca9916f}, intrahash = {64999648cce3bbfbf430f299751321d9}, isbn = {978-1-60558-837-7}, keywords = {dblp}, pages = {689-694}, publisher = {IEEE}, timestamp = {2019-10-17T16:46:10.000+0200}, title = {Minimizing leakage power in aging-bounded high-level synthesis with design time multi-Vth assignment.}, url = {http://dblp.uni-trier.de/db/conf/aspdac/aspdac2010.html#ChenXWT10}, year = 2010 }