%0 Conference Paper %1 conf/vlsid/ShrivastavaPOC13 %A Shrivastava, Aatmesh %A Pandey, Jagdish Nayayan %A Otis, Brian P. %A Calhoun, Benton H. %B VLSI Design %D 2013 %I IEEE Computer Society %K dblp %P 72-75 %T A 50nW, 100kbps Clock/Data Recovery Circuit in an FSK RF Receiver on a Body Sensor Node. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2013.html#ShrivastavaPOC13 %@ 978-1-4673-4639-9

@inproceedings{conf/vlsid/ShrivastavaPOC13, added-at = {2023-03-24T00:00:00.000+0100}, author = {Shrivastava, Aatmesh and Pandey, Jagdish Nayayan and Otis, Brian P. and Calhoun, Benton H.}, biburl = {https://www.bibsonomy.org/bibtex/265680a6547b8438a29f6788c8e6ed57a/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2013}, ee = {https://doi.ieeecomputersociety.org/10.1109/VLSID.2013.165}, interhash = {9d3af9137a156ca97fba0fe76933d3b5}, intrahash = {65680a6547b8438a29f6788c8e6ed57a}, isbn = {978-1-4673-4639-9}, keywords = {dblp}, pages = {72-75}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:08:28.000+0200}, title = {A 50nW, 100kbps Clock/Data Recovery Circuit in an FSK RF Receiver on a Body Sensor Node.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2013.html#ShrivastavaPOC13}, year = 2013 }