Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction
MICRO 36: Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, page 81. Washington, DC, USA, IEEE Computer Society, (2003)Abstract
This paper proposes and evaluates single-ISA heterogeneousmulti-core architectures as a mechanism to reduceprocessor power dissipation. Our design incorporatesheterogeneous cores representing different points inthe power/performance design space; during an application'sexecution, system software dynamically chooses themost appropriate core to meet specific performance andpower requirements.Our evaluation of this architecture shows significant energybenefits. For an objective function that optimizes forenergy efficiency with a tight performance threshold, for 14SPEC benchmarks, our results indicate a 39% average energyreduction while only sacrificing 3% in performance.An objective function that optimizes for energy-delay withlooser performance bounds achieves, on average, nearly afactor of three improvement in energy-delay product whilesacrificing only 22% in performance. Energy savings aresubstantially more than chip-wide voltage/frequency scaling.
Description
Single-ISA Heterogeneous Multi-Core Architectures
