%0 Journal Article %1 mehra2010based %A Mehra, Rajesh %A Devi, Swapna %D 2010 %E Das, Dr. Vinu V %J International Journal on Signal & Image Processing %K ASIC DALUT FPGA MAC SDR %N 2 %P 5 %T FPGA Based Design of High Performance Decimator using DALUT Algorithm %U http://doi.searchdl.org/01.IJSIP.1.2.02 %V 1 %X This paper presents a multiplier less approach to implement high speed and area efficient decimator for down converter of Software Defined Radios. This technique substitutes multiply-and-accumulate (MAC) operations with look up table (LUT) accesses. Proposed decimator has been implemented using Partitioned distributed arithmetic look up table (DALUT) algorithm by taking optimal advantage of embedded LUTs of target FPGA device. This method is useful to enhance the system performance in terms of speed and area. The proposed decimator has used half band polyphase decomposition FIR structure. The decimator has been designed with Matlab 7.6, simulated with Modelsim 6.3XE simulator, synthesized with Xilinx Synthesis Tool (XST) 10.1 and implemented on Spartan-3E based 3s500efg320-4 FPGA device. The proposed DALUT approach has shown an improvement of 24% in speed by saving almost 50% resources of target device as compared to MAC based approach.

@article{mehra2010based, abstract = {This paper presents a multiplier less approach to implement high speed and area efficient decimator for down converter of Software Defined Radios. This technique substitutes multiply-and-accumulate (MAC) operations with look up table (LUT) accesses. Proposed decimator has been implemented using Partitioned distributed arithmetic look up table (DALUT) algorithm by taking optimal advantage of embedded LUTs of target FPGA device. This method is useful to enhance the system performance in terms of speed and area. The proposed decimator has used half band polyphase decomposition FIR structure. The decimator has been designed with Matlab 7.6, simulated with Modelsim 6.3XE simulator, synthesized with Xilinx Synthesis Tool (XST) 10.1 and implemented on Spartan-3E based 3s500efg320-4 FPGA device. The proposed DALUT approach has shown an improvement of 24% in speed by saving almost 50% resources of target device as compared to MAC based approach.}, added-at = {2012-10-03T09:42:32.000+0200}, author = {Mehra, Rajesh and Devi, Swapna}, biburl = {https://www.bibsonomy.org/bibtex/27233184672c937ab88f65802302872f8/ideseditor}, editor = {Das, Dr. Vinu V}, interhash = {969a87b8f87eaa9cca1138fe1db50768}, intrahash = {7233184672c937ab88f65802302872f8}, journal = {International Journal on Signal & Image Processing }, keywords = {ASIC DALUT FPGA MAC SDR}, month = {July}, number = 2, pages = 5, timestamp = {2012-10-03T09:42:32.000+0200}, title = {FPGA Based Design of High Performance Decimator using DALUT Algorithm}, url = {http://doi.searchdl.org/01.IJSIP.1.2.02}, volume = 1, year = 2010 }