The most radical of the architectures that appear in this issue are Raw processors-highly parallel architectures with hundreds of very simple processors coupled to a small portion of the on-chip memory. Each processor, or tile, also contains a small bank of configurable logic, allowing synthesis of complex operations directly in configurable hardware. Unlike the others, this architecture does not use a traditional instruction set architecture. Instead, programs are compiled directly onto the Raw hardware, with all units told explicitly what to do by the compiler. The compiler even schedules most of the intertile communication. The real limitation to this architecture is the efficacy of the compiler. The authors demonstrate impressive speedups for simple algorithms that lend themselves well to this architectural model, but whether this architecture will be effective for future workloads is an open question
Description
IEEE Xplore Abstract - Baring it all to software: Raw machines
%0 Journal Article
%1 raw
%A Waingold, E.
%A Taylor, M.
%A Srikrishna, D.
%A Sarkar, V.
%A Lee, W.
%A Lee, V.
%A Kim, J.
%A Frank, M.
%A Finch, P.
%A Barua, R.
%A Babb, J.
%A Amarasinghe, S.
%A Agarwal, A.
%D 1997
%J Computer
%K PAP1
%N 9
%P 86-93
%R 10.1109/2.612254
%T Baring it all to software: Raw machines
%U http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=612254&tag=1
%V 30
%X The most radical of the architectures that appear in this issue are Raw processors-highly parallel architectures with hundreds of very simple processors coupled to a small portion of the on-chip memory. Each processor, or tile, also contains a small bank of configurable logic, allowing synthesis of complex operations directly in configurable hardware. Unlike the others, this architecture does not use a traditional instruction set architecture. Instead, programs are compiled directly onto the Raw hardware, with all units told explicitly what to do by the compiler. The compiler even schedules most of the intertile communication. The real limitation to this architecture is the efficacy of the compiler. The authors demonstrate impressive speedups for simple algorithms that lend themselves well to this architectural model, but whether this architecture will be effective for future workloads is an open question
@article{raw,
abstract = {The most radical of the architectures that appear in this issue are Raw processors-highly parallel architectures with hundreds of very simple processors coupled to a small portion of the on-chip memory. Each processor, or tile, also contains a small bank of configurable logic, allowing synthesis of complex operations directly in configurable hardware. Unlike the others, this architecture does not use a traditional instruction set architecture. Instead, programs are compiled directly onto the Raw hardware, with all units told explicitly what to do by the compiler. The compiler even schedules most of the intertile communication. The real limitation to this architecture is the efficacy of the compiler. The authors demonstrate impressive speedups for simple algorithms that lend themselves well to this architectural model, but whether this architecture will be effective for future workloads is an open question},
added-at = {2016-01-22T13:46:02.000+0100},
author = {Waingold, E. and Taylor, M. and Srikrishna, D. and Sarkar, V. and Lee, W. and Lee, V. and Kim, J. and Frank, M. and Finch, P. and Barua, R. and Babb, J. and Amarasinghe, S. and Agarwal, A.},
biburl = {https://www.bibsonomy.org/bibtex/278bfe55a85bbdc7b9ae73cf1c78194fd/ross_mck},
description = {IEEE Xplore Abstract - Baring it all to software: Raw machines},
doi = {10.1109/2.612254},
interhash = {489e1fe4177cb728e4d09953f2a1d7a5},
intrahash = {78bfe55a85bbdc7b9ae73cf1c78194fd},
issn = {0018-9162},
journal = {Computer},
keywords = {PAP1},
month = sep,
number = 9,
pages = {86-93},
timestamp = {2016-01-22T13:46:02.000+0100},
title = {Baring it all to software: Raw machines},
url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=612254&tag=1},
volume = 30,
year = 1997
}