%0 Conference Paper %1 conf/vlsid/HeZTM07 %A He, Wei-Feng %A Zhao, Meng-Lian %A Tsui, Chi-Ying %A Mao, Zhi-Gang %B VLSI Design %D 2007 %I IEEE Computer Society %K dblp %P 830-835 %T A Scalable Frame-Level Pipelined Architecture for FSBM Motion Estimation. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2007.html#HeZTM07 %@ 0-7695-2762-0

@inproceedings{conf/vlsid/HeZTM07, added-at = {2023-03-24T00:00:00.000+0100}, author = {He, Wei-Feng and Zhao, Meng-Lian and Tsui, Chi-Ying and Mao, Zhi-Gang}, biburl = {https://www.bibsonomy.org/bibtex/27f3ac16dce2e9553a88ac4e6c217724a/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2007}, ee = {https://doi.ieeecomputersociety.org/10.1109/VLSID.2007.26}, interhash = {63a627320750c8ebfe454674611269cd}, intrahash = {7f3ac16dce2e9553a88ac4e6c217724a}, isbn = {0-7695-2762-0}, keywords = {dblp}, pages = {830-835}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:18:09.000+0200}, title = {A Scalable Frame-Level Pipelined Architecture for FSBM Motion Estimation.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2007.html#HeZTM07}, year = 2007 }