%0 Journal Article %1 journals/ejasp/Torres-HuitzilA05 %A Torres-Huitzil, César %A Arias-Estrada, Miguel O. %D 2005 %J EURASIP J. Adv. Signal Process. %K dblp %N 7 %P 1024-1034 %T FPGA-Based Configurable Systolic Architecture for Window-Based Image Processing. %U http://dblp.uni-trier.de/db/journals/ejasp/ejasp2005.html#Torres-HuitzilA05 %V 2005

@article{journals/ejasp/Torres-HuitzilA05, added-at = {2020-03-12T00:00:00.000+0100}, author = {Torres-Huitzil, César and Arias-Estrada, Miguel O.}, biburl = {https://www.bibsonomy.org/bibtex/281ce0bdba628ade1ae786cd3bbdcba6e/dblp}, ee = {https://doi.org/10.1155/ASP.2005.1024}, interhash = {93965c89d85e27d912e164f6436bc815}, intrahash = {81ce0bdba628ade1ae786cd3bbdcba6e}, journal = {EURASIP J. Adv. Signal Process.}, keywords = {dblp}, number = 7, pages = {1024-1034}, timestamp = {2020-03-13T12:15:56.000+0100}, title = {FPGA-Based Configurable Systolic Architecture for Window-Based Image Processing.}, url = {http://dblp.uni-trier.de/db/journals/ejasp/ejasp2005.html#Torres-HuitzilA05}, volume = 2005, year = 2005 }