%0 Conference Paper %1 conf/vlsi/ChampacRG15 %A Champac, Víctor H. %A ha Reyes, Alejandra Nicte %A Gomez, Andres F. %B VLSI-SoC %D 2015 %I IEEE %K dblp %P 165-170 %T Circuit performance optimization for local intra-die process variations using a gate selection metric. %U http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2015.html#ChampacRG15 %@ 978-1-4673-9140-5

@inproceedings{conf/vlsi/ChampacRG15, added-at = {2017-05-24T00:00:00.000+0200}, author = {Champac, Víctor H. and ha Reyes, Alejandra Nicte and Gomez, Andres F.}, biburl = {https://www.bibsonomy.org/bibtex/2832344942b563fb05d644d3685347533/dblp}, booktitle = {VLSI-SoC}, crossref = {conf/vlsi/2015soc}, ee = {https://doi.org/10.1109/VLSI-SoC.2015.7314410}, interhash = {61c0680390cf2789987025e16a78f0b0}, intrahash = {832344942b563fb05d644d3685347533}, isbn = {978-1-4673-9140-5}, keywords = {dblp}, pages = {165-170}, publisher = {IEEE}, timestamp = {2019-10-17T14:01:58.000+0200}, title = {Circuit performance optimization for local intra-die process variations using a gate selection metric.}, url = {http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2015.html#ChampacRG15}, year = 2015 }