%0 Conference Paper %1 conf/dtis/Dasygenis14 %A Dasygenis, Minas %B DTIS %D 2014 %I IEEE %K dblp %P 1-2 %T A web EDA tool for the automatic generation of synthesizable VHDL architectures for a rapid design space exploration. %U http://dblp.uni-trier.de/db/conf/dtis/dtis2014.html#Dasygenis14 %@ 978-1-5090-0336-5

@inproceedings{conf/dtis/Dasygenis14, added-at = {2014-08-14T00:00:00.000+0200}, author = {Dasygenis, Minas}, biburl = {https://www.bibsonomy.org/bibtex/2892019f8d805d71f249b60f2dfca8bc0/dblp}, booktitle = {DTIS}, crossref = {conf/dtis/2014}, ee = {http://dx.doi.org/10.1109/DTIS.2014.6850659}, interhash = {89c4cef0dde11d8527539610a2becbff}, intrahash = {892019f8d805d71f249b60f2dfca8bc0}, isbn = {978-1-5090-0336-5}, keywords = {dblp}, pages = {1-2}, publisher = {IEEE}, timestamp = {2016-06-04T11:53:02.000+0200}, title = {A web EDA tool for the automatic generation of synthesizable VHDL architectures for a rapid design space exploration.}, url = {http://dblp.uni-trier.de/db/conf/dtis/dtis2014.html#Dasygenis14}, year = 2014 }