%0 Conference Paper %1 conf/fpga/ZhuangYJHJH0024 %A Zhuang, Jinming %A Yang, Zhuoping %A Ji, Shixin %A Huang, Heng %A Jones, Alex K. %A Hu, Jingtong %A Shi, Yiyu %A Zhou, Peipei %B FPGA %D 2024 %E Zhang, Zhiru %E Putnam, Andrew %I ACM %K dblp %P 55-66 %T SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration. %U http://dblp.uni-trier.de/db/conf/fpga/fpga2024.html#ZhuangYJHJH0024

@inproceedings{conf/fpga/ZhuangYJHJH0024, added-at = {2024-04-15T00:00:00.000+0200}, author = {Zhuang, Jinming and Yang, Zhuoping and Ji, Shixin and Huang, Heng and Jones, Alex K. and Hu, Jingtong and Shi, Yiyu and Zhou, Peipei}, biburl = {https://www.bibsonomy.org/bibtex/28bc9d6f4d6b1409e84fec16ab7b10f22/dblp}, booktitle = {FPGA}, crossref = {conf/fpga/2024}, editor = {Zhang, Zhiru and Putnam, Andrew}, ee = {https://doi.org/10.1145/3626202.3637569}, interhash = {255f7d9ca9ddf3059cae2e2da00f22d3}, intrahash = {8bc9d6f4d6b1409e84fec16ab7b10f22}, keywords = {dblp}, pages = {55-66}, publisher = {ACM}, timestamp = {2024-04-22T07:46:05.000+0200}, title = {SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration.}, url = {http://dblp.uni-trier.de/db/conf/fpga/fpga2024.html#ZhuangYJHJH0024}, year = 2024 }