%0 Conference Paper %1 conf/aspdac/WandelerT06 %A Wandeler, Ernesto %A Thiele, Lothar %B ASP-DAC %D 2006 %E Hirose, Fumiyasu %I IEEE %K dblp %P 479-484 %T Optimal TDMA time slot and cycle length allocation for hard real-time systems. %U http://dblp.uni-trier.de/db/conf/aspdac/aspdac2006.html#WandelerT06 %@ 0-7803-9451-8

@inproceedings{conf/aspdac/WandelerT06, added-at = {2018-11-06T00:00:00.000+0100}, author = {Wandeler, Ernesto and Thiele, Lothar}, biburl = {https://www.bibsonomy.org/bibtex/29d5a3c79eb4bdd037eb8b618039f39c9/dblp}, booktitle = {ASP-DAC}, crossref = {conf/aspdac/2006}, editor = {Hirose, Fumiyasu}, ee = {https://doi.org/10.1145/1118299.1118417}, interhash = {a380492866a4e68cc1551c64351ce5b5}, intrahash = {9d5a3c79eb4bdd037eb8b618039f39c9}, isbn = {0-7803-9451-8}, keywords = {dblp}, pages = {479-484}, publisher = {IEEE}, timestamp = {2019-10-17T16:45:43.000+0200}, title = {Optimal TDMA time slot and cycle length allocation for hard real-time systems.}, url = {http://dblp.uni-trier.de/db/conf/aspdac/aspdac2006.html#WandelerT06}, year = 2006 }