%0 Journal Article %1 journals/jssc/WuCL07 %A Wu, Patrick Y. %A Cheung, Vincent Sin-Luen %A Luong, Howard C. %D 2007 %J IEEE J. Solid State Circuits %K dblp %N 4 %P 730-738 %T A 1-V 100-MS/s 8-bit CMOS Switched-Opamp Pipelined ADC Using Loading-Free Architecture. %U http://dblp.uni-trier.de/db/journals/jssc/jssc42.html#WuCL07 %V 42

@article{journals/jssc/WuCL07, added-at = {2020-08-30T00:00:00.000+0200}, author = {Wu, Patrick Y. and Cheung, Vincent Sin-Luen and Luong, Howard C.}, biburl = {https://www.bibsonomy.org/bibtex/2b57abcd8c7e0e469928712038713876a/dblp}, ee = {https://doi.org/10.1109/JSSC.2007.891666}, interhash = {f5d9bf2bc89874093ecb83f6c6b2dd97}, intrahash = {b57abcd8c7e0e469928712038713876a}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 4, pages = {730-738}, timestamp = {2020-08-31T11:42:47.000+0200}, title = {A 1-V 100-MS/s 8-bit CMOS Switched-Opamp Pipelined ADC Using Loading-Free Architecture.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc42.html#WuCL07}, volume = 42, year = 2007 }